Several difficulties can appear when testing receivers and device input ports; including the difficulty in accessing how well the test signal was received. This is even more challenging when one is prohibited from or lacks easy access to information collected by the receiver at the input port of the device under test. A known way around this is to set the device under test in a loop back mode where all or some of the input port signal information is returned in either raw or processed format via one of the device under test's output ports. However such known ways work best when the test equipment and the device under test are operated in a synchronous manner. If the clocks of the test apparatus and the device under test are not synchronous then byte(s) of the signal or data may be deleted or inserted by the device under test (DUT) in order to prevent overflow or accumulation of data or signal information. Many devices further decode, encode or otherwise process the signals or data that are looped back. If signals or data are incorrectly aligned when decoding and/or encoding then the looped back signal or data will differ from the expected value.
One such example is the electrical 10 bit to 8 bit (10 b/8 b) decoding and 8 bit to 10 bit (8 b/10 b) encoding used in high speed digital communications such as Fibre Channel, PCI-express and Serial ATA; if the first of the 10 data bits is not aligned then a different and perhaps invalid 8 bit word would be the outcome with possible errors as a result. Hence in the example there could be twenty different outcomes equivalent to the ten possible misalignments multiplied with the 2 different disparities that errors may cause.
In creating alignment, often various tests are required. These tests are conventionally complicated by the need for a priori knowledge of the functionality of the DUT. For example, sometimes knowledge about specialized connections or control software is needed. Other times there is a need to repeat the setting of the DUT into various test modes for each desirable test pattern, data or signal.